Electrostatic discharge (ESD) refers to a phenomenon wherein a charged device of a given potential suddenly discharges carriers to a separate device of lower potential. The discharge occurs over a short time frame and, therefore, results in a momentary large current, if the resistance of the discharge path is kept low. For example, a human walking over a carpet in an environment of low humidity can collect electrostatic charge, and build up an electrostatic potential of several thousands volts. If the charged human touches a semiconductor device, an electrostatic discharge takes place from the human to elements of the semiconductor device. Such discharges can damage the semiconductor device unless means are provided for clamping the large voltages and diverting the currents resulting from the electrostatic discharge.
A known double diode protective circuit is shown in FIG. I wherein one diode 2 is tied between input terminal 16 and an upper supply voltage VDD of a semiconductor device and the other diode 4 is tied between the input terminal 16 and ground. When an input signal is received with a voltage potential greater than VDD, diode 2 turns on for clamping the excessive input signal to the upper supply VDD. Likewise, if the input signal received has a voltage potential less than ground i.e. -0.6 V, diode 4 turns on to clamp the excessive input signal to -0.6 V. The diodes assure that the input signal is clamped within a diode drop between ground and near VDD preventing excessive potentials from damaging circuitry of the semiconductor device beyond output terminal 18. However, the two diodes are not suitable for mixed voltage applications.
In mixed voltage interfacing applications, it is common for an input signal to have voltage levels greater than the positive supply of the receiving semiconductor device. For example, it may be required for a receiving device to convert input signals of 0 volts and 5 volts to output signals of 0 volts and 3 volts respectively. In such applications it is desirable to clamp the input between 0 volts and 5 volts instead of 0 volts and 3 volts, the levels of the receiving device. Thus, the input protection circuit should provide input limiting when the input voltage is in excess of 5 volts, which is 2 volts above the 3 volt positive supply of the receiving device. Zener type operation is desired wherein the input signal is clamped when it is at least 2 volts beyond the upper supply voltage of the receiving device.
With reference to FIG. 2, a known electrostatic discharge protection circuit comprises two shunting N-FETs (i.e. N channel MOSFETs) 10, 12 separated by a series resistor 14. The first FET 10 has it drain and gate connected to input terminal 16 and its source coupled to ground. Series resistor 14 is in a series path between input terminal 16 and output terminal 18 and separates the two shunting FETs 10 and 12. The second FET 12 has its drain coupled to output terminal 18, and its source and gate coupled to ground. The insulating oxide layer for the gate of the first shunting FET 10 is thick while the oxide layer for the gate of the second shunting FET 12 is thin. The thick oxide provides the first FET a larger threshold voltage in contrast to the second FET. The threshold voltage for the first FET is set per the oxide thickness to be several volts above the positive supply of the semiconductor device. In contrast, the thin oxide for the second FET provides the FET a minimal threshold voltage and breakdown voltage so that it breaks down before the first FET turns on when a positive potential ESD event is applied to the input terminal. However, problems with the protection circuit of FIG. 2 concern a failure mode due to excessive power dissipation within the first and second shunting FETs, and process complexity in obtaining the desired threshold voltage for the first shunting FET 10.
For N-FET devices, when avalanche breakdown results, the electrons injected into a depletion region of a reverse biased function acquire sufficient energy to create new carriers when colliding with silicon atoms of the depletion region and a sudden increase in reverse leakage current results. Typical FET devices have sufficient drain and source resistance values (ballasting resistance) to provide voltage drops that stabilize the avalanche condition and reverse leakage current. However, with self-aligned silicide devices--wherein the gate, drain and source layers have self-aligned titanium heated with the silicon layers thereof to provide silicide of lower sheet resistance--the resistance values are much lower. However, the silicide sheet resistance can be non-uniform. With low, non-uniform resistance (minimal ballasting resistance) localized heating results in the depletion region of the reverse biased junction. The localized heating creates a bipolar positive feedback phenomenon wherein more carriers are generated in the depletion region to provide increased reverse current. As this process continues, thermal-run-away progresses until thermal damage results.